This invention relates to a logic circuit such as an OR/NOR circuit, an XOR/XNOR circuit, a selector circuit or a latch circuit, and more particularly to a logic circuit which can operate at a high speed with a low power supply voltage.
A demand to lower the operating voltage of a logic circuit is increasing from the point of view of refinement of a process or reduction of power consumption. Thus, a configuration of a conventional differential circuit which is a basic logic circuit is described first, and then restriction conditions to lower the operating voltage are described.
An example of circuit configuration of a differential circuit wherein a bipolar element is used is shown in FIG. 13. Referring to FIG. 13, the differential circuit shown includes differential pair transistors Q201 and Q202 whose emitters are connected commonly, a current source I201 connected between the emitter common connecting point of the differential pair transistors Q201 and Q202 and the ground, and a pair of resistors R201 and R202 connected between the collectors of the differential pair transistors Q201 and Q202 and a power supply line (power supply voltage VCC), respectively.
A circuit of a form which includes the differential circuit or a modification to the differential circuit is generally referred to as ECL (Emitter Coupled Logic) circuit. It is to be noted that the following argument applies substantially similarly to a circuit which employs a MOS element. In the differential circuit shown in FIG. 13, a differential signal AP/AN inputted to the input terminals of the differential circuit determines a differential signal ZP/ZN from output terminals of the differential circuit. Although the logic operation of the differential circuit normally is that of a buffer circuit, actually the differential circuit otherwise operates also as a NOT circuit depending upon the correspondence between the signal levels and the logic values.
For example, if the relationship AP greater than AN between the potentials AP and AN at the input terminals corresponds to the xe2x80x9ctruexe2x80x9d of the logic value and the relationship ZP greater than ZN between the potentials ZP and ZN at the output terminals corresponds to the xe2x80x9ctruexe2x80x9d of the logic value, then the circuit of FIG. 13 operates as a mere buffer circuit. On the other hand, if the logic correspondence of the input or the output is reversed, for example, if ZP greater than ZN corresponds to the xe2x80x9cfalsexe2x80x9d of the logic value, then the same circuit now operates as a NOT circuit.
It is to be noted that this is a common technique used in configuration of a logic circuit which uses a differential signal. In other words, the logic reversal (NOT) can be implemented only by connecting a differential signal reversely.
Since a differential circuit by itself in most cases has an insufficient driving capacity for a load, an emitter follower is often added to an output stage of the differential circuit. In particular, referring to FIG. 14, the differential circuit shown in FIG. 13 additionally includes a series circuit of a transistor Q203 and a current source I202 and another series circuit of a transistor Q204 and a current source I203 connected in parallel to each other between the power supply line and the ground. The bases of the transistors Q203 and Q204 are connected to the collectors of the differential pair transistors Q201 and Q202, respectively, and a differential output is derived from the emitters of the transistors Q203 and Q204.
Where the configuration wherein the emitter follower transistors Q203 and Q204 are added to the output stage of the differential circuit in this manner is adopted, the output logic level drops by the base-emitter voltage VBE of the emitter follower transistors Q203 and Q204. Since a conventional ECL circuit uses a comparatively high voltage around 4.5 V as such power supply voltage VCC, the drop of such a voltage as mentioned above does not matter very much.
One of advantages of an ECL circuit is that, since it uses a technique of series gating or wired ORing of emitter followers, various logic functions can be realized without so much increasing the delay of a signal. In the following, several examples of such circuit are described.
The first example is a series gate AND circuit, and a circuit configuration of it is shown in FIG. 15. It is to be noted that, in FIG. 15, like elements to those of FIG. 13 are denoted by like reference characters. Referring to FIG. 15, the series gate AND circuit includes differential pair transistors Q205 and Q206 provided on the ground side with respect to the differential pair transistors Q201 and Q202 and having the emitters connected commonly.
The collector of the transistor Q205 is connected to the emitter common connecting point of the differential pair transistors Q201 and Q202, and the collector of the transistor Q206 is connected to the ZP side output terminal together with the collector of the transistor 0202. Further, the current source I201 is connected between the emitter common connecting point of the differential pair transistors Q205 and Q206 and the ground.
In the AND circuit having the configuration described above, where the potentials at the input terminals of the A system are represented by AP and AN and the potentials at the input terminals of the B system by BP and BN while the potentials at the output terminals by ZP and ZN, ZP  greater than ZN is satisfied only when AP  greater than AN and BP  greater than BN.
This condition can be written by a logic formula as
Z=ABxe2x80x83xe2x80x83(1) 
In the expression (1), the xe2x80x9ctruexe2x80x9d of the logic variable xe2x80x9cAxe2x80x9d is allocated to the state of AP  greater than AN. This similarly applies to xe2x80x9cBxe2x80x9d and xe2x80x9cZxe2x80x9d. The mark xe2x80x9cxe2x80x9d represents the logic AND.
Here, in order to prevent the transistor Q205 from being saturated, it is required that the signal level of the B system side be lower than that of the A system side. Although multi-stage series gating is possible with an ECL circuit, as the number of stages increases, a correspondingly lower logic level is required. Consequently, the number of stages of possible series gating is restricted.
Where the De Morgan theorem is used, the negation of the both sides of the expression (1) is given by
!Z=(AB)=!A!Bxe2x80x83xe2x80x83(2) 
where xe2x80x9c!xe2x80x9d represents the reversal of the logic, and xe2x80x9cxe2x80x9d represents the logic OR. The expression (2) indicates that, if the correspondence of the inputs/outputs to the logic values is reversed, then the same circuit functions as a logic OR circuit.
As another method for realizing the logic OR, a wired OR connection or a collector dot is known. An example of OR circuit which employs a wired OR connection and a collector dot is shown in FIG. 16. Referring to FIG. 16, like elements to those of FIG. 14 are denoted by like reference characters, and the circuit shown in FIG. 16 adopts a quite same configuration of a differential circuit as that of FIG. 14 in which it has an emitter follower configuration at an output stage thereof.
Meanwhile, the emitter common connecting point of the differential pair transistors Q205 and Q206 is connected to the ground through a current source I204. The collector of the transistor Q205 is connected to the collector of the transistor Q201. The connecting point between the two collectors is a collector dot. Meanwhile, the collector of the transistor Q206 is connected to the power supply line through a resistor R203.
The base of a transistor Q207 is connected to the collector of the transistor Q206. The collector of the transistor Q207 is connected to the power supply line, and the emitter of the transistor Q207 is connected commonly to the emitter of the transistor Q204. The connection of the emitters is a wired OR connection and connected to the ground through the current source I203.
In the circuit configuration described above, the potential ZP at the output terminal connected to the wired OR connection depends upon a higher one of base voltages at the transistor Q204 and the transistor Q207, but is lower by the base-emitter voltage VBE than the higher base voltage. Therefore, if the state wherein the base potential is higher is regarded as logic true, then the wired OR connection acts as a logic OR circuit.
A wired OR connection can be modified to accept multiple inputs readily, and to this end, it is only required to merely connect emitter follower outputs of n ECL circuits. The number n of ECL circuits may be a considerable great number, and, for example, n=8 can be permitted sufficiently. If an excessively great number of transistors are connected by a wired OR connection, then this gives rise to a problem that not only the parasitic capacitance becomes so high as to make the circuit operation slow but also the DC amplitude becomes small.
Since a reversed signal cannot be produced merely by a wired OR connection, in order to obtain a differential output, a circuit called collector dot described above is used frequently in combination with a wired OR connection. Since the potential at the collector common connecting point of the transistors Q201 and Q205 which is a collector dot exhibits a high level when both of the transistors Q201 and Q205 are off, the negation of the wired OR is produced.
The low level of the potential at the collector dotting differs depending upon whether only one of the transistors Q201 and Q205 is on or both of them are on. If an n-input logic circuit is produced directly in this manner, then the low level is separated into n different levels and has an n-fold amplitude at the maximum. This amplitude variation is unsuitable for high-speed operation, and in order to prevent the low level from becoming excessively low, a diode is sometimes connected in parallel to a resistor. However, the clipping voltage in this instance in most cases becomes excessively high.
A latch circuit which employs an ECL circuit popularly uses a latched comparator circuit configuration. An example of circuit configuration of a latched comparator circuit is shown in FIG. 17.
Referring to FIG. 17, the latched comparator circuit shown includes differential pair transistors Q301 and Q302 whose emitters are connected commonly, differential pair transistors Q303 and Q304, and differential pair transistors Q305 and Q306. The collectors of the differential pair transistors Q301 and Q302 are connected to a power supply Vcc through resistors R301 and R302, respectively.
The collector and the base of the transistor Q303 are connected to the collectors of the differential pair transistors Q301 and Q302, respectively, and the collector and the base of the transistor Q304 are connected to the collectors of the transistor Q302 and Q301, respectively. The collectors of the differential pair transistors Q305 and Q306 are connected to the emitter common connecting points of the differential pair transistors Q301 and Q302 and the differential pair transistors Q303 and Q304, respectively. The emitter common connecting point of the differential pair transistors Q305 and Q306 is connected to the ground through a current source I301.
When the potential CLKN at a clock input terminal of the latch circuit having such a latched comparator circuit configuration as described above keeps the high level, the transistor Q305 is on, and the latch circuit acts as a buffer. When the potential CLKP at the other clock input terminal of the latch circuit changes from the low level to the high level, the gain of the differential pair transistors Q301 and Q302 decreases gradually, and states of the potentials ZP and ZN at output terminals of the latch circuit at the point of time are inherited to a latch circuit (positive feedback circuit) formed from the differential pair transistors Q303 and Q304.
Now, it is examined to which level the power supply voltage VCC can be lowered with an ECL circuit. If the input signal level to the circuit shown in FIG. 13 is at the VCC level, then the emitter potential of the differential pair transistors Q201 and Q202 is VCCxe2x88x92VBE. Where the lowest operation enabling voltage of the current source I201 is represented by VTC, it is necessary to satisfy the following expression (3):
VCCxe2x88x92VBE greater than VTCxe2x80x83xe2x80x83(3) 
Actually, since a margin equal to approximately one half (depending upon the signal waveform) of the logic amplitude VSW of the input signal is necessary, the condition to determine the lowest operating voltage for the differential pair is given by
VCC greater than VBE+(VSW/2)+VTCxe2x80x83xe2x80x83(4) 
In the emitter follower of FIG. 14, since the logic amplitude VSW has an influence directly on the operating voltage of the current source I202, the lowest operating voltage is a little more severer and given by
VCC greater than VBE+VSW+VTCxe2x80x83xe2x80x83(5) 
However, where the output of the circuit of FIG. 14 drives a differential pair in the next stage, the condition for the power supply voltage VCC becomes severer by an amount corresponding to the base-emitter voltage VBE. The reason is that, as can be recognized from an imaginary connection of the output terminals to the input terminals of the circuit of FIG. 14, the emitter potential of the differential pair transistors Q201 and Q202 becomes equal to VCCxe2x88x922VBE, and therefore, the condition given by
VCC greater than 2VBE+(VSW/2)+VTCxe2x80x83xe2x80x83(6) 
is required. In particular, although the emitter follower can operate itself in the proximity of the lowest power supply voltage of the ECL circuit, it can not drive anything. In other words, the power supply voltage of the expression (4) merely allows adoption of a logic configuration of direct coupling of a differential pair.
Now, a series gating of transistors is considered. Referring to FIG. 15, the emitter potential of the differential pair transistors Q201 and Q202 is VCCxe2x88x92VBE at the highest. The emitter potential of the transistors Q203 and Q204 must be lower than VCCxe2x88x92VBExe2x88x92VSAT if the lowest VSAT (saturation voltage) with which the transistors can operate is assured. Therefore, the condition is given by
VCC greater than VBE+VSAT+(VSW/2)+VTCxe2x80x83xe2x80x83(7) 
Where a logic circuit is formed from an ECL circuit, the restriction provided by the expression (4) is very severe because it allows formation only of a buffer. The restriction provided by the expression (7) seems to be a limit for practical use. Quantitatively, for a bipolar element, VBExe2x89xa10.9 V (when the temperature is low), VSAT xe2x89xa10.3 V, VSWxe2x89xa10.2 V, and VTCxe2x89xa10.5 V or so. By substituting the values into the expression (7),
VCC greater than 1.8 Vxe2x80x83xe2x80x83(8) 
is determined as an operation limit of a bipolar ECL circuit.
Various means are required to configure a logic circuit which achieves the limit voltage given above. First, in order to use the limit of the saturation voltage VSAT, a potential lower by the saturation voltage VSAT than the power supply voltage VCC is required as an operation point of the B system side of FIG. 15. This can be realized by configuring a level shift circuit which includes, for example, as shown in FIG. 18, a resistor R204 connected between power supply side end portions of the resistors R201 and R201 and the power supply line such that, where the resistance value of the resistor R204 is represented by R and the current value of the current source I201 is represented by I, Rxe2x80xa2I=VSAT may be satisfied.
In the level shift circuit of the configuration described above, it is required that the differential pair transistors Q201 and Q202 be not saturated with the input potential to the A system side. In order to satisfy the requirement, according to circumferences, it is necessary to connect a plurality of such circuits as shown in FIG. 18 in series gating in several stages to gradually lower the signal level.
It is another problem in achievement of the expression (7) that an emitter follower cannot be used. In order to increase the driving capacity, it is necessary to increase the current of the differential circuit. This, however, increases the number of input fan-ins. In order to drive many loads, after all it is obliged to connect a plurality of buffers of differential pairs in successive stages. This increases not only current consumption but also the number of elements. In this manner, the fact that an emitter follower cannot be used imposes a heavy burden in circuit design.
A logic circuit for a low voltage is disclosed in U.S. Pat. No. 4,845,387. The logic circuit is not up-to-date in that it requires a special element such as a Schottky diode. Further, a systematic logic circuit system is disclosed in U.S. Pat. No. 5,289,055. The logic circuit system is characterized in that it operates at a comparatively high speed when the load is low.
However, since the logic circuit system uses two sets of logic levels in its essential part, the circuit operates substantially in single operation. Accordingly, in order to assure a DC margin of a signal, the logic amplitude must be set greater than that of a differential circuit. This is disadvantageous in speed and also in lowering of a power supply voltage. In a circuit wherein the logic circuit system is used for a latch, a rising/falling waveform or phase displacement of a differential signal of a clock has a significant influence on the latch characteristic. Therefore, the circuit is inferior in repeatability of operation and cannot be used readily as a component of a large scale logic circuit.
It is an object of the present invention to provide a high-speed logic circuit which has a sufficient load driving capacity even in its operation with a low power supply voltage.
In order to attain the object described above, according to the present invention, there is provided a logic circuit comprising a drive circuit having an output stage of an emitter follower configuration or a source follower configuration, and a folding circuit including a transistor of a diode connection having a first terminal (for example, the emitter or the source) connected to an emitter follower output terminal or source follower output terminal of the drive circuit and a second terminal (for example, the collector or the drain) connected to a power supply line through a resistor.
In the logic circuit, the folding circuit in which the transistor of a diode connection is used is provided in the next stage to the differential circuit whose output stage has the emitter follower configuration (or source follower configuration) The transistor of a diode connection (the diode of the logic level) acts to raise the signal level of the emitter follower output (or source follower output) by a voltage corresponding to a voltage between the base and the emitter (or between the gate and the source) of the transistor. In this instance, since both of the transistor of the emitter follower (or source follower) and the transistor of a diode connection are normally in an on-state, the folding circuit operates at a very high speed similarly to an ordinary emitter follower (or source follower). Consequently, the logic circuit can operate at a very high speed with a sufficient load driving capacity even in operation with a low power supply voltage.